1. Field of the Invention
The present invention relates to a current measuring structure for testing integrated circuits.
2. Discussion of the Related Art
Integrated circuits are tested at various stages in the course of production. Tests include wafer testing (often referred to as EWS--Electrical Wafer Sort) in which the whole wafer (semiconductor slice in which various devices are integrated) is tested prior to separating the chips; and final testing of the separate chips mounted in the respective packages.
In the case of power integrated circuits, the wafer test provides, among other things, for measuring various high currents, which are subsequently related to similar currents measured at the final test stage. A typical example is measurement of the current value triggering the current limiting circuit with which the power stages are normally provided.
The above measurement is critical regarding both forcing the current and acquiring measuring data, due to the high-energy voltage peaks ("spikes") produced by high currents in the presence of parasitic inductance caused by the measuring devices. Moreover, at the high current levels involved, the pad sensors are subject to severe wear, thus resulting in gradual aging of the measurement with time; and, finally, problems are encountered in relating the wafer and final test measurements, due to differing power dissipation conditions.
To reduce the criticalness of the measurement and to overcome the aforementioned drawbacks, a known practice for wafer testing is to measure a current lower than, but related to, the normal operating current. To demonstrate this approach, FIG. 1 shows a known solution relative to a power stage with a d.c. current limiting circuit. The following account also applies to other solutions featuring switch-operated limiting circuits, by virtue of both types being based on current-voltage conversion by a calibrated resistor for generating a voltage proportional to the current through the power stage.
In FIG. 1, the power stage and the limiting circuit are shown schematically. The power stage, which forms part of integrated circuit 1a, includes a power MOS transistor 2 supplied at the drain terminal by current source 3; and the limiting stage 4 comprises an operational amplifier 5, the output of which is connected to the drain terminal of transistor 2 for limiting the current supplied to transistor 2, and the two inputs of which are connected to the two terminals of a sensing resistor 6 series connected to the source terminal of transistor 2. In particular, the negative input of amplifier 5 is connected to the common node between the drain terminal of transistor 2 and a first terminal of resistor 6; and the positive input of amplifier 5 is connected to the other terminal of resistor 6 through a voltage source 7 supplying voltage V.sub.R.
Resistor 6 of limiting circuit 4 normally consists of a suitably sized metal strip, and has an accurately known resistance R.sub.s normally ranging between a few tens and a few hundred m.OMEGA., for reducing both power dissipation and the voltage drop in series with the power stage, so that Voltage drop V.sub.1 at the terminals of resistor 6 is generally on the order of a hundred mV at most.
In the FIG. 1 circuit, limiting stage 4 is operated when V.sub.1 .apprxeq.V.sub.R, i.e. when current I.sub.L through transistor 2, and consequently resistor 6 equals: EQU I.sub.L =V.sub.R /R.sub.s ( 1)
One technique for determining operation of the limiting circuit at less than the nominal current provided during normal operation of the integrated circuit includes reducing voltage V.sub.R supplied by source 7 during the wafer test stage. Such a reduction, which may be achieved in various ways has several basic drawbacks affecting correct correlation of the wafer and final test measurements, and thus resulting in problems in terms of electrical yield.
The major problem posed by the above approach relates to the voltage Offset of operational amplifier 5. To-obtain a limit current for wafer testing reduced by a scaling factor of 10, for example, in relation to the nominal value, Equation (1) indicates that V.sub.R must also be reduced by the same scaling factor to obtain values on the order of about 10 mV. As operational amplifiers normally employed for such applications have an offset of 1-2 mV, an excessively high measuring spread of 10-20% results. Accordingly, this known approach is only feasible in the case of very low scaling factors, thus reducing the advantages to be gained.
Furthermore, as the V.sub.R reduction factor increases, measuring repeatability decreases, due to a reduction in V.sub.R, emphasizing inaccuracy due to noise.